This invention relates generally to semiconductor devices to more particularly to semiconductor devices having shallow trench isolation.
As is known in the art, active devices formed in semiconductor integrated circuits are electrically isolated by a dielectric. One technique to isolate devices formed in a silicon substrate is to form silicon dioxide regions between the devices. One technique is sometimes referred to as a local oxidation (LOCOS) process wherein exposed areas of the silicon are oxidized to form field oxide region between the devices. In another technique, a so-called shallow trench isolation (STI) technique, shallow trenches are formed in the exposed areas of the silicon and are then filled with a dielectric, typically TEOS. Prior to filling the trenches, a thin layer of silicon dioxide is thermally grown over the surface including sidewalls of the trenches. Next, a thin layer is silicon nitride is chemically vapor deposited over the silicon dioxide. A layer of TEOS is then deposited over the silicon nitride, portions of the TEOS filling the trench. The structure then typically undergoes a wet anneal during densification of the TEOS. The silicon nitride layer is used to prevent oxygen produced during the wet anneal from entering the silicon. That is, the silicon nitride prevents oxidation of the silicon trench sidewalls; otherwise, such oxidation would tend to create unwanted stresses and crystal dislocations in the silicon. The upper portions of the TEOS are removed to expose the portions of the surface of the silicon adjacent to STI region. The surface of the silicon is oxidized to form a gate oxide. Doped polycrystalline silicon is then formed over the gate oxide and photolithographically patterned into gate electrodes for MOSFET devices being formed.
As is also known in the art, some integrated circuits use both p-channel on n-channel MOSFETs. For example, in a DRAM, an array of memory cells is provided in one region of the circuit and auxiliary circuitry, such as addressing and logic circuitry, are formed in another region of the circuit, for example around the periphery of the array region. One type of DRAM cell includes a MOSFET connected to a buried, or trench capacitor. As noted above, absent the nitride liner along the sidewalls of the STI trench, the silicon sidewalls of the trench may become oxidized during the wet anneal used to densify the TEOS. This oxidation will cause stresses and dislocations in the silicon thereby reducing charge retention time by the DRAM cell, Thus, a silicon nitride layer is formed on the isolation trench sidewalls to protect the silicon sidewalls. Further, while the MOSFETs used in the array may be n-FET devices, the auxiliary circuits may include p-FET devices. Still further, in order to use the same type doping for the polycrystalline silicon used for both the p-MOSFETs and n-MOSFETs while both type MOSFET have substantially the same work function, a buried channel MOSFET is used for the p-MOSFET devices.